Typically, a memory device that stores data is largely classified as either a volatile semiconductor memory device or a nonvolatile semiconductor memory device. The volatile memory device principally represented as a DRAM (Dynamic Random Access Memory) or a SRAM (Static Random Access Memory), etc. is fast with regard to the input/output operation of data, but has a shortcoming in that stored contents are lost when a power supply is stopped. The nonvolatile memory device principally represented as EPROM (Erasable Programmable Read Only Memory) or EEPROM(Electrically Erasable Programmable Read Only Memory), etc. is slow with regard to the input/output operation of data, but has the benefit of maintaining the stored data intact even when a power supply is interrupted.
A conventional memory device is commonly employing a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) based-memory. For example, a stack gate-type transistor memory device of a stack structure adapted on a semiconductor substrate formed of silicon material, and a trench gate type transistor memory device having a structure buried in the inside of the semiconductor substrate, are under development. However, a width and length of channel in the MOSFET must be formed with a sufficient length to suppress a short-channel effect. Further, a thickness of a gate insulation layer formed between a gate electrode formed on the channel and the semiconductor substrate must be extremely thin. Due to this fundamental problem, there is a difficulty to realize a memory device having a nano-level ultra microstructure for the MOSFET.
Memory devices of the structure to replace the MOSFET with new ones are under active research. Recently, micro electromechanical system (MEMS) and nano electromechanical system (NEMS) technology applied to suspend bridge memory (SBM) has been represented. An example of a nonvolatile memory device using the MEMS technology is disclosed in U.S. Pat. No. 6,054,745, incorporated herein by reference.
FIG. 1 is a sectional view schematically showing a conventional memory device.
As shown in FIG. 1, a conventional memory device is obtained by forming an FET (Field Effect Transistor) sensor 221, attractive electrode part 223, and cantilever electrode supporter 225, to be distinguished from one another, on a shallow trench isolation(STI) 224 formed on a substrate 222. A cantilever electrode 240 is further formed of a type such that one side of the cantilever electrode 240 is supported by, and electrically connected to, the cantilever electrode supporter 225, wherein the cantilever electrode 240 is distanced by a predetermined height from the attractive electrode part 223 and the FET sensor 221. The cantilever electrode 240 is formed so as to be curved toward the attractive electrode 232 by an electric field induced by the attractive electrode part 223. Then, even when the electric field induced by the attractive electrode part 223 is eliminated, the cantilever electrode 240 can maintain its curved state by an electric field induced from electrons captured by a polysilicon gate electrode 230 of the FET sensor 221. For example, the polysilicon gate electrode 230 corresponds to a floating electrode of a flash memory device, which captures electrons that tunnel through a tunnel oxide layer that is formed of a dielectric formed on a source-drain region 227 of the FET sensor 221. The attractive electrode part 223 and the cantilever electrode supporter 225 are formed of the same polysilicon material as the polysilicon gate electrode 230. The cantilever electrode 240 is also formed of polysilicon material like the cantilever electrode supporter 225.
That is, in a conventional memory device, a nonvolatile memory device can include an attractive electrode 232 for curving the cantilever electrode 240 by an electromagnetic force, and an FET sensor 221 including the gate electrode 230 for maintaining the curved state of the cantilever electrode 240, in a lower part of the cantilever electrode 240.
However, a conventional memory device has the following problems.
In the conventional memory device, a high voltage must be applied between the cantilever electrode 240 and the attractive electrode 232 so as to endure tension of the cantilever electrode 240 supported by the cantilever electrode supporter 225, in permitting contact between the cantilever electrode 240 and the attractive electrode 232.
Further, in the conventional memory device, the cantilever electrode supporter 225 and the FET sensor 221 are formed in parallel at the same level. Thus, it is difficult to arrange a matrix type cell array and so there is a shortcoming in that an integration of memory devices decreases.
Further, in the conventional memory device, the attractive electrode part 223 causes the cantilever electrode 240 of a horizontal state to be curved, and the FET sensor 221 maintains the curved state of the cantilever electrode 240 that is curved by the attractive electrode part 223. Thus, the attractive electrode part 223 and FET sensor 221 must be configured on the same horizontal face, but separately from each other, and the cantilever electrode 240 must be formed long to cover the upper part of the attractive electrode part 223 and the FET sensor 221. Therefore, a limitation exists with regard to a decrease in integration of memory devices.
Further, in the conventional memory device, data of only 1 bit is programmed or read out per single unit cell comprising the cantilever electrode 240, attractive electrode 232 and FET sensor 221, and thus, it is difficult to store multibit data.